Currículum Vitae

Elisardo Antelo Suárez

November 2006

Contact Information:
Dept. Electrónica e Computación.
University of Santiago de Compostela.
15782 Santiago de Compostela. SPAIN.
Email: elisardo@dec.usc.es
Office phone: +34 981594488x13577.
Business cell: +34 619848049.
Fax: +34 528012

Personal Data

• Date and Place of Birth: January 30th, 1968, in Ames, Spain.
• Marital Status: Married, one child.
• Citizenship: Spanish.
• Current position: Associate Professor (permanent position).
• Department: Electrónica y Computación.
• University: Universidade de Santiago de Compostela. SPAIN

Education

• B.Sc. in Physics, University of Santiago de Compostela (Spain), 1991.
• Ph.D. in Computer Eng., University of Santiago de Compostela (Spain), 1995. Title: CORDIC Algorithms and Architectures with redundant arithmetic for high-speed processing, Advisor: Dr. Javier Díaz Bruguera.

Research Interest

Digital design and computer architecture with current emphasis on high-speed and low-power numerical processors, application-specific modules, computer arithmetic and analytical models for the design of multi-core processors

Employment

• 1998-present: Associate Professor (Profesor Titular de Universidad in the Spanish University system). Dept. Electronica e Computacion, University of Santiago de Compostela (Spain). Permanent position.
• 1992-1998: Assistant Professor. Dept. Electronica e Computacion, University of Santiago de Compostela (Spain). Permanent position.

Teaching Activities

Dedication: 1992- to present, average of 200 hours of classes per academic year

• Graduate Level: about 300 hours. Computer Arithmetic, Numerical Processors Design, CAD Tools for Design and Synthesis of Electronic Circuits, Digital Signal and Video Processors, Methodologies for Electronic Design, Microprocessors Architecture and Technology.
• Upper Undergraduate Level: about 2000 hours. Medicine applications of Electronics, Digital Electronics, Electronic Devices, Microelectronics, Electronics, Advanced Digital Design, Computer Technology, Computer Architecture, Parallel and Distributed Systems.
• Lower Undergraduate Levels: about 500 hours. Fundamentals of Digital Systems, Computer Systems Fundamentals, Programming.

Supervision of Graduate Research Works

• M. Vicente Lozano, "Design of a CORDIC Unit extended for the computation of inverse trigonometric functions''. Graduation thesis, 1997.
• José María Calo Domínguez, "VLSI Implementation of a CORDIC architecture for angle calculation and rotation''. Graduation thesis, 1997.
• Álvaro VázquezÁlvarez , ``Implementation of the exponential function in a floating-point unit'', Graduation thesis, 1999.
• Álvaro VázquezÁlvarez, ``Combined division/square-root/reciprocal square-root unit for 3D graphics geometry processing''. Master Thesis, 2002.
• Álvaro VázquezÁlvarez, ``High-performance Decimal Floating-Point Units'', PhD. Thesis, 2007 (expected).

Projects for Innovation in Education

Participation in three projects between 2002-2005 for the integration of on-line contents in the Virtual Campus of the University of Santiago de Compostela.

Awards

• Research Initiation Award from the Xunta de Galicia (Local Government). 1999.
• First Contest on Ideas for Technology Spin-Offs. First Prize. Organizers: University of Santiago de Compostela and Xunta de Galicia. 2001.
• First Contest on Technology Spin-offs projects . Third Prize. Organizers: University of Santiago de Compostela and Xunta de Galicia. 2002.

Research Associates

• T. Lang, University of California at Irvine (USA), 1994-present.
• J. Villalba, University of Malaga (Spain), 1993-present.
• P. Montuschi, Politecnico di Torino, Italy, 2001-present.
• A. Nannarelli, Technical University of Denmark, Denmark, 2001-present.

Research Visitor

• Department of Electrical and Computer Engineering (Numerical Processors group). Three months, 1996. Topic: Development of arithmetic algorithms based on recurrences.
• Department of Electrical and Computer Engineering (Numerical Processors group). Two months, 1998. Topic: Very-high radix CORDIC algorithms.
• Department of Electrical and Computer Engineering (Numerical Processors group). One month, 2000. Topic: Combined unit for division, square root and reciprocal square root.

Professional Societies

• IEEE and IEEE Computer Society.
• SARTECO (Spanish Computer Architecture and Technology Association).

Professional Services

Conferences

• Local arrangements for VII Jornadas de Paralelismo. Santiago de Compostela, Spain, September 11-13, 1996.
• Program Committee Member, 15th IEEE Symposium on Computer Arithmetic, Vail, USA, June 2001.
• Program Committee Member, 17th IEEE Symposium on Computer Arithmetic, Cape Cod, USA, June 2005.
• Publicity Chair, 17th IEEE Symposium on Computer Arithmetic, Cape Cod, USA, June 2005.
• Program Committee Member, 7th Real Numbers and Computers Conference, Nancy, France, July 2006.
• Program Committee Member, 18th IEEE Symposium on Computer Arithmetic, Montpelier, France, June 2007.

Reviewer

• Reviewer for Journals: IEEE Transactions on Computers, IEEE Transactions on Circuits and Systems, IEEE Transactions on CAD, IEE Proceedings - Digital Techniques, IEE Electronic Letters, Journal of VLSI Signal Processing, Signal Processing.
• Reviewer for Conferences: ARITH-14 (14th IEEE Symposium on Computer Arithmetic, Adelaida, Australia, 1999), ARITH-15 (14th IEEE Symposium on Computer Arithmetic, Vail, Colorado, USA, 2001), ARITH-17 (17th IEEE Symposium on Computer Arithmetic, Cape Cod, MA, USA, 2005), RNC'7 (7th Conf. on Real Numbers and Computers, Nancy, France, July 2006), ARITH-18 (18th IEEE Symposium on Computer Arithmetic, Montpelier, France, June 2007).
• External Reviewer for Research Evaluation in the area of specialized processor for the Universidad of Aman, Jordan (año 2003).
• Reviewer for Research Projects for ANEP (Agencia Nacional de Evaluación y Prospectiva - Spanish Agency for Evaluation of Research).

Funded Research

• Science and Technology Council of SPAIN, Contract CICYT ref. TIC92-0942-C03-03: ``Massively Parallel Computation. VLSI Architectures Design'', 1992-1995. PI: Dr. Javier Díaz Bruguera. 90.000 Euros.
• Science and Technology Council of SPAIN, Contract CICYT ref. TIC96-1125-C03-02: ``Architectures and Compilers for massively parallel comptuation: dynamic applications and/or based on sparse matrices'', 1996-1999. PI: Dr. Javier Díaz Bruguera. 96.000 Euros.
• Xunta de Galicia and FEDER (European Commission), Contract PGIDT 99PXI20601A: ``Algorithms and Arithmetic Units for 3D Computer Graphics and Animation''. 1999-2002. PI: Elisardo Antelo Suárez. 31.000 Euros.
• Science and Technology Council of SPAIN, Contract CICYT ref. TIC2001-3694-C02-01: ``High-Performance Computation for Rendering applications''. 2001-2004. PI: Dr. Javier Díaz Bruguera. 240.000 Euros.
• State of California (MICRO Program) and Synopsys Inc., Contract MICRO 01-047: ``Hardware Support for Geometric Transformations in 3D Graphics, Animation and Virtual Reality'', 2001-2002. PI: Dr. Tomás Lang.
• Xunta de Galicia and FEDER (European Commission), Contract PGIDIT03TIC10502PR: ``Development of software/hardware Systems for 3D graphics, animation and virtual reality''. 2003-2006. PI: Montserrat Bóo Cepeda. 18.000 Euros.
• Science and Technology Council of SPAIN, Contract CICYT ref. TIN2004-07797-C02-02: ``Middleware and hardware solutions for high-performance computing: applications to multimedia and simulation''. 2004-2007. PI: Dr. Javier Díaz Bruguera. 233.000 Euros.

Publications

Translations

E. Antelo. O Computador e o Cerebro. Translation to Galego of the book ``The Computer and the Brain'' by John Von Neumann. 2006. ISBN 84-9750-526-3. Published by University of Santiago de Compostela and BBVA Foundation.

International Journals

1. J.D. Bruguera, E. Antelo and E.L. Zapata. Design of a Pipelined Radix-4 CORDIC Processor. J. Parallel Computing. Vol. 19., pp. 729-744. (1993).

2. E. Antelo, J.D. Bruguera and E.L. Zapata. Unified Mixed Radix 2-4 Redundant CORDIC Processor. IEEE Transactions on Computers. Vol. 45, no. 9, pp. 1068-1073, Sept. 1996.

3. E. Antelo, J. Villalba, J.D. Bruguera and E.L. Zapata. High Performance Rotation Architectures Based on the Radix-4 CORDIC Algorithm.IEEE Transactions on Computers, Vol. 46, no. 8, pp. 855-870, August 1997.

4. E. Antelo, J.D. Bruguera, T. Lang and E.L. Zapata. Error Analysis and Reduction for Angle Calculation Using the CORDIC Algorithm.IEEE Transactions on Computers. Vol. 46, no 11, pp. 1264-1271, Nov. 1997.

5. E. Antelo, T. Lang and J.D. Bruguera. Computation of sqrt(x/d) in a Very High-Radix Combined Division/Square-root Unit with Scaling and Selection by Rounding. IEEE Transactions on Computers. Vol. 47, no 2, pp. 152-161, Feb. 1998.

6. E. Antelo, M. Bóo, J.D. Bruguera and E.L. Zapata. A Novel Design of a Two Operand Normalization Circuit. IEEE Transactions on Very Large Scale of Integration (VLSI) Systems. Vol. 6, no 1, pp. 173-176, March 1998.

7. J. Villalba, E.L. Zapata, E. Antelo and J.D. Bruguera, Radix-4 Vectoring CORDIC Algorithm and Architectures. J. of VLSI Signal Processing for Signal, Image and Video Technology. Vol 20, no 2 , pp. 127-147, July 1998.

8. T. Lang and E. Antelo. CORDIC Vectoring with Arbitrary Target Value. IEEE Transactions on Computers - Special Section: Papers from the 13th Symposium on Computer Arithmetic, Vol. 47, no 7, pp. 736-749, July 1998.

9. T. Lang and E. Antelo. CORDIC-Based Computation of ArcCos and sqrt(1-t^2). Journal of VLSI Signal Processing for Signal, Image and Video Technology, Vol. 25, no 1, pp. 19-38, May 2000.

10. E. Antelo, T. Lang and J.D. Bruguera. Very-High Radix CORDIC Rotation Based on Selection by Rounding. Journal of VLSI Signal Processing for Signal, Image and Video Technology - Special Issue on CORDIC, Vol. 25, no 2, pp. 141-153, June 2000.

11. E. Antelo, T. Lang and J.D. Bruguera. Very-High Radix Circular CORDIC: Vectoring and Unified Rotation/Vectoring. IEEE Transactions on Computers - Special Issue on Computer Arithmetic, Vol 49, no 7, pp. 727-739, July 2000.

12. A. Vázquez and E. Antelo. Implementation of the Exponential Function in a Floating-Point Unit. Journal of VLSI Signal Processing for Signal, Image and Video Technology - Special issue on Computer Arithmetic and Applications, Vol. 33, no 1/2, pp. 125-145, Jan. 2003.

13. T. Lang amd E. Antelo. Radix-4 Reciprocal Square-Root and Its Combination with Division and Square Root. IEEE Transactions on Computers, Vol 52, no 9, pp. 1100-1114, Sept. 2003.

14. T. Lang and E. Antelo. High-Throughput CORDIC-Based Geometry Operations for 3D Computer Graphics. IEEE Transactions on Computers - Special Issue on Computer Arithmetic, Vol 54, no 3, pp. 347-361, March 2005.

15. E. Antelo, T. Lang, P. Montuschi and A. Nannarelli. Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Transactions on Computers, Vol 54, no 7, pp. 837-851, July 2005.

Conference Proceedings

1. M. Bóo, E. Antelo and J.D. Bruguera VLSI Implementation of an Edge Detector Based on Sobel Operator. Proc. Euromicro'94. Liverpool, UK. pp. 506-512, 1994.

2. E. Antelo, J.D. Bruguera and E.L. Zapata. Unnormalized Fixed-Point CORDIC Arithmetic for SVD Processors. Proc. Int. Conf. on Signal Processing, Applications and Technology. ICSPAT'94. Dallas, USA. pp. 1725-1730, 1994.

3. R. Osorio, E. Antelo, J.D. Bruguera, J. Villalba and E.L. Zapata. Digit On-Line Large Radix CORDIC Rotator. Proc. IEEE Int. Conf. Application Specific Array Processors. ASAP'95. Strasbourg, France. pp. 246-257, 1995.

4. J. Villalba, J.A. Hidalgo, E. Antelo, J.D. Bruguera and E.L. Zapata. CORDIC Architectures with Parallel Compensation of the Scale Factor Proc. IEEE Int. Conf. Application Specific Array Processors. ASAP'95. Strasbourg, France. pp. 258-269, 1995.

5. E. Antelo, J.D. Bruguera, J. Villalba and E.L. Zapata. Redundant CORDIC Rotator based on Parallel Prediction. Proc. IEEE 12th Symp. Computer Arithmetic. ARITH'12. Bath. U.K. pp. 172-179, 1995.

6. J. Villalba, J.C. Arrabal, E. Antelo, J.D. Bruguera and E.L. Zapata. Radix-4 Vectoring CORDIC Algorithm and Architectures. Proc. IEEE Int. Conf. Application Specific Systems, Architecures, and Processors. ASAP'96. Chicago, USA. pp. 55-64, August 1996.

7. E. Antelo, J.D. Bruguera, T. Lang, J. Villalba and E.L. Zapata. High Radix CORDIC Rotation Based on Selection by Rounding.Lecture Notes in Computer Science (Europar'96: Parallel Processing, Workshop: Parallel Image/Video Processing and Computer Arithmetic), Lyon, France, pp. 155-164, August 1996.

8. T. Lang and E. Antelo. CORDIC vectoring with arbitrary target value. En Proc. 13th IEEE Symposium on Computer Arithmetic. ARITH'13, Asilomar, USA, pp. 108-115, July 1997.

9. T. Lang y E. Antelo. CORDIC-based computation of arcos and arcsin. En Proc. 11th IEEE International Conference on Application-specific Systems, Architectures and Processors. ASAP'97, Zurich, Switzerland, pp. 132-143, July 1997.

10. J.M. Calo, E. Antelo and J.D. Bruguera. VLSI Implementation of an Architecture for Angle Computation and Rotation.Proc. XII Design of Circuits ad Integrated Systems Conference. DCIS'97. Sevilla, Spain, pp. 765-770, Nov. 1997.

11. E. Antelo, T. Lang and J.D. Bruguera. Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. Proc. 14th IEEE Symposium on Computer Arithmetic. ARITH'14, Adelaide, Australia, pp. 204-213, April 1999.

12. J.-A Piñeiro, E. Antelo and J.D. Bruguera. Circuit Implementation of a Very-High Radix CORDIC Vectoring Algorithm of Angle Calculation. Proc. XIV Conf. Design of Integrated Circuits and Systems. DCIS'99, pp. 189-194, Palma de Mallorca, Spain, Nov. 1999.

13. T. Lang and E. Antelo. Correctly Rounded Reciprocal Square Root by Digit Recurrence and Radix-4 Implementation. Proc. 15th IEEE Symposium on Computer Arithmetic. ARITH'15, Vail, USA, pp. 83-93, June 2001.

14. T. Lang and E. Antelo. High-Performance 3D Rotations and Normalizations. Proc. 35th IEEE Asilomar Conference on Systems and Computers, Asilomar, USA, Nov. 2001.

15. E. Antelo, T. Lang, P. Montuschi y A. Nannarelli. Fast Retimed radix-4 Division with Selection by Comparisons. Proc. 13th IEEE International Conference on Application-Specific Systems, Architectures and Processors, San Jose, USA, pp. 185-196, Julio 2002.

16. E. Antelo, T. Lang, P. Montuschi and A. Nannarelli. Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. Proc. 17th IEEE Symposium on Computer Arithmetic. ARITH'17, Cape Cod, USA, pp. 147-154, June 2005.

17. E. Antelo and J. Villalba. Low Latency Pipelined Circular CORDIC. Proc. 17th IEEE Symposium on Computer Arithmetic. ARITH'17, Cape Cod, USA, pp. 280-287, June 2005.

18. A. Vázquez and E. Antelo. Conditional Speculative Decimal Addition. Proc. 7th Conf. on Real Numbers and Computers. RNC'7, Nancy, France, pp. 47-57, July 2006.